1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor package and a method of fabricating the same.
2. Description of the Related Art
Recently, the production of Package-on-package (PoP) products, in which multiple packages are stacked, has increased to meet demand for miniaturization and desired functionality of mobile electronic devices. Conventionally, a semiconductor package that performs one function is mounted in each of the mobile electronic devices. Also, in order to realize high capacity and multi-functional products, products that perform more than two package functions in one package size, by stacking multiple packages that perform different functions, for example, have been increasingly produced.
FIGS. 1A through 1C are cross-sectional views of a conventional PoP structure. More specifically, FIG. 1A is a cross-sectional view of an upper package 10a of the conventional PoP structure, and FIG. 1B is a cross-sectional view of a lower package 10b of the conventional PoP structure.
Referring to FIG. 1A, in the upper package 10a, more than one semiconductor chip 12a is stacked on a substrate 11a by interposing adhesion layers 13a therebetween. The semiconductor chips 12a are electrically connected to the substrate 11a by bonding wires 14a. A sealing member 15a that seals the semiconductor chips 12a and the bonding wires 14a is formed on an entire top surface of the substrate 11a. Solder balls 16a are formed on a bottom surface of the substrate 11a to electrically connect the substrate 11a to external elements outside of the upper package 10a. 
Referring to FIG. 1B, in the lower package 10b, more than one semiconductor chip 12b is stacked on a substrate 11b by interposing adhesion layers 13b therebetween. The semiconductor chips 12b are electrically connected to the substrate 11b by bonding wires 14b. A sealing member 15b that seals the semiconductor chips 12b and the bonding wires 14b is formed on a top surface of the substrate 11b. If the size of the semiconductor chips 12b is small, the sealing member 15b may not cover the entire top surface of the substrate 11b. Solder balls 16b are formed on a bottom surface of the substrate 11b to electrically connect the substrate 11b to external elements outside of the lower package 10b. 
FIG. 1C is a cross-sectional view of the conventional PoP structure.
Referring to FIG. 1C, the upper package 10a is stacked on the lower package 10b. It is unfavorable to stack the upper package 10a on the lower package 10b since an overall height of the conventional PoP is increased. The upper package 10a and the lower package 10b are electrically connected to each other by contacting the solder balls 16a of the upper package 10a with the top surface of the substrate 11b of the lower package 10b. Also, the solder balls 16b of the lower package 10b can be electrically connected to external elements. Thus, the upper package 10a is supported by its solder balls 16a, which are on the substrate 11b of the lower package 10b, and thus, an overall structure is structurally weak. That is, a crack or a bending phenomenon can occur in the substrate 11b of the lower package 10b due to an external impact or weight.
FIG. 2A is an electron microscope picture of a crack generated in a conventional PoP structure, and FIG. 2B is a photo image of a bending phenomenon in a conventional PoP structure.
Referring to FIG. 2A, the figure shows that the crack occurs in a region A_1 of a substrate of a lower package due to an external impact. Referring to FIG. 2B, the figure shows that the bending occurs in a region A_2 of a substrate of a lower package when there is an external impact.
In order to prevent the substrate from cracking and bending, the thickness of the substrate of the lower package can be increased or a sealing member can be formed to cover an entire top surface of the substrate of the lower package, however, these methods undesirably increase an overall height of the entire conventional PoP.